Image processing apparatus, control method therefor and storage medium

ABSTRACT

When the first time has elapsed after the operator operates a power switch to stop power supply, an image processing apparatus forcibly stops power supply. When stopping power supply, the image processing apparatus executes hibernation processing to retract, in a secondary storage device, the stored content of a main memory used as a work area by a CPU. When the hibernation processing will be completed within a target time necessary to complete the hibernation processing and end processing of the image processing apparatus before the first time elapses, the image processing apparatus executes the end processing of the image processing apparatus and stops power supply after completing the hibernation processing; otherwise, the image processing apparatus interrupts the hibernation processing, executes the end processing of the image processing apparatus, and stops power supply.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image processing apparatus, controlmethod therefor, and storage medium.

2. Description of the Related Art

Along with the development of high performance technology, current imageprocessing apparatuses tend to take a longer startup time until theybecome operable after the user turns on the power switch. To solve this,there is a method of shortening the startup time by a suspend methodwhich energizes a main memory when the user performs a power-offoperation. However, when the main memory is a general DRAM or the like,the suspend method needs to continue energization, increasing standbypower. A technique for reducing standby power to zero is a hibernationmethod. The hibernation method is a technique employed to furtherimprove power saving performance though it takes a longer return timethan that in the suspend method. For example, Japanese Patent Laid-OpenNo. 2002-73220 discloses a technique of assigning a physical powerswitch (toggle switch) having an OFF/ON state as the hibernationfunction. Japanese Patent Laid-Open No. 11-3151 discloses a technique ofperforming a hibernation operation when the battery is running out. Atthis time, even if the battery runs out, this technique avoids power-offduring the hibernation shift.

However, the conventional techniques have the following problems. Forexample, in Japanese Patent Laid-Open No. 2002-73220, the power switchof the image processing apparatus is a (toggle) switch having a physicalOFF/ON state, so the OFF/ON state of the switch and the power OFF/ONstate of the main body need to coincide with each other. That is, astate in which the power supply of the main body remains ON though theswitch is OFF should not occur. To prevent this, when the power switchis turned off, a protection timer needs to be set in the power supplydevice separately from software control to guarantee that the powersupply will be turned off without fail after a predetermined time.However, when the power switch is assigned as the hibernation function,if hibernation shift processing is not completed in time, the powersupply is forcibly turned off based on the protection timer during thehibernation shift.

SUMMARY OF THE INVENTION

The present invention enables realization of a mechanism of safelyexecuting hibernation shift processing even in an arrangement whichturns off the power supply without fail a predetermined time afterturning off the power switch, and preferably shortening the time tillthe stop of power supply.

One aspect of the present invention provides an image processingapparatus which forcibly stops power supply when a first time haselapsed after an operator operates a power switch to stop power supply,comprising: a processing unit that executes hibernation processing toretract, in a secondary storage device, a stored content of a mainmemory used as a work area by a CPU of the image processing apparatuswhen stopping power supply to the image processing apparatus; adetermination unit that determines whether or not the hibernationprocessing by the processing unit will be completed within a target timenecessary to complete the hibernation processing and end processing ofthe image processing apparatus before the first time elapses; and apower control unit that, when the hibernation processing is determinedto be completed within the target time, executes the end processing ofthe image processing apparatus and stops power supply after theprocessing unit completes the hibernation processing, and when thehibernation processing is determined not to be completed within thetarget time, interrupts the hibernation processing by the processingunit, executes the end processing of the image processing apparatus, andstops power supply.

Another aspect of the present invention provides a method forcontrolling an image processing apparatus which forcibly stops powersupply when a first time has elapsed after an operator operates a powerswitch to stop power supply, comprising: causing a processing unit toexecute hibernation processing to retract, in a secondary storagedevice, a stored content of a main memory used as a work area by a CPUof the image processing apparatus when stopping power supply to theimage processing apparatus; causing a determination unit to determinewhether or not the hibernation processing in the causing the processingunit to execute the hibernation processing will be completed within atarget time necessary to complete the hibernation processing and endprocessing of the image processing apparatus before the first timeelapses; and causing a power control unit to, when the hibernationprocessing is determined to be completed within the target time, executethe end processing of the image processing apparatus and stop powersupply after completing the hibernation processing in the causing theprocessing unit to execute the hibernation processing, and when thehibernation processing is determined not to be completed within thetarget time, interrupt the hibernation processing in the causing theprocessing unit to execute the hibernation processing, execute the endprocessing of the image processing apparatus, and stop power supply.

Further features of the present invention will be apparent from thefollowing description of exemplary embodiments with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view exemplifying the arrangement of an image processingsystem according to an embodiment;

FIG. 2 is a block diagram exemplifying the arrangement of a controlleraccording to the embodiment;

FIG. 3 is a view exemplifying the arrangement of a power supplyaccording to the embodiment;

FIG. 4 is a flowchart showing a processing sequence in shutdownaccording to the embodiment;

FIG. 5 is a view for explaining hibernation according to the embodiment;

FIG. 6 is a flowchart showing a processing sequence in systeminterruption according to the embodiment;

FIG. 7 is a view showing a secondary storage device according to theembodiment;

FIG. 8 is a timing chart showing a normal case and a case in which atrouble occurs;

FIG. 9 is a timing chart according to the embodiment;

FIG. 10 is a timing chart showing a system protection timer according tothe embodiment; and

FIG. 11 is a flowchart showing a processing sequence according to theembodiment.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will now be described in detailwith reference to the drawings. It should be noted that the relativearrangement of the components, the numerical expressions and numericalvalues set forth in these embodiments do not limit the scope of thepresent invention unless it is specifically stated otherwise.

<Arrangement of Image Processing Apparatus>

The arrangement of an image processing system in an embodiment will bedescribed with reference to FIG. 1. As shown in FIG. 1, the imageprocessing system includes an image processing apparatus 100, and acomputer 109 connected to the image processing apparatus 100 via a LAN108. Note that this system arrangement is merely an example, and is notintended to limit the present invention. For example, the imageprocessing system may include another image processing apparatus andanother computer.

The image processing apparatus 100 includes a scanner device 102,controller 103, printer device 104, operation unit 105, hard disk 106,and FAX device 107. The scanner device 102 optically reads an image froman original and converts it into a digital image. The printer device 104outputs a digital image onto a paper medium. The operation unit 105 isan interface for operating the image processing apparatus 100 by theuser. The hard disk 106 stores digital images, control programs, and thelike. The FAX device 107 transmits a digital image to a telephone lineor the like, and receives a digital image from the telephone line or thelike. The controller 103 is connected to the above-described modules,and executes a job on the image processing apparatus 100 by issuinginstructions to the respective modules.

The image processing apparatus 100 can, for example, receive/output adigital image from/to the computer 109 via the LAN 108, and issue a joband an instruction to a device. The scanner device 102 includes adocument feed unit 121 capable of automatically changing a bundle oforiginals in sequence, and a scanner unit 122 capable of opticallyscanning an original and converting it into a digital image. The scannerdevice 102 transmits converted image data to the controller 103. Theprinter device 104 includes a paper feed unit 142 capable ofsequentially feeding sheets one by one from a sheet bundle, a markingunit 141 for printing image data on a fed sheet, and a discharge unit143 for discharging a printed sheet.

The image processing apparatus 100 can execute various jobs. Examplesare as follows:

Copy function

An image read from the scanner device 102 is recorded on the hard disk106, and at the same time, printed using the printer device 104.

Image transmission function

An image read from the scanner device 102 is transmitted to the computer109 via the LAN 108.

Image save function

An image read from the scanner device 102 is recorded on the hard disk106, and if necessary, transmitted and printed.

Image print function

For example, a page description language transmitted from the computer109 is analyzed and printed by the printer device 104.

<Arrangement of Controller>

The arrangement of the controller 103 will be exemplified with referenceto FIG. 2. The controller 103 includes a main board 200 and sub-board220. The main board 200 is a so-called general-purpose CPU system, andincludes a CPU 201, boot ROM 202, memory 203, bus controller 204,nonvolatile memory 205, disk controller 206, flash disk 207, USBcontroller 208, and timer 210. The CPU 201 performs centralized controlof the overall board. The boot ROM 202 stores a boot program serving asa program used in initial startup. The memory 203 is a main memory usedas a work area by the CPU 201. The bus controller 204 has a bridgefunction with an external bus. The nonvolatile memory 205 is a memorywhich does not lose the stored contents even upon power-off. The diskcontroller 206 controls a storage device. The flash disk (for example,SSD) 207 is a relatively-small-capacity storage device formed from asemiconductor device. The USB controller 208 controls a USB device (USBmemory 209 in this case). The timer 210 is a system protection timerfunctioning as a timer means. The USB memory 209, operation unit 105,hard disk 106, and the like are connected to the main board 200 from theoutside.

The sub-board 220 is formed from a relatively-small general-purpose CPUsystem and image processing hardware. The sub-board 220 includes a CPU221, a memory 223, a bus controller 224, a nonvolatile memory 225, animage processing unit 227, and device controllers 226 and 228. The CPU221 performs centralized control of the overall board. The memory 223 isused as a work memory by the CPU 221. The bus controller 224 has abridge function with an external bus. The nonvolatile memory 225 doesnot lose the stored contents even upon power-off. The image processingunit 227 performs real-time digital image processing. The devicecontrollers 228 and 226 exchange digital image data with the externalscanner device 102 and printer device 104, respectively. Note that theCPU 221 directly controls the FAX device 107.

FIG. 2 is a simplified block diagram. For example, the CPU 201, CPU 221,and the like include many CPU peripheral hardware modules such as a chipset, bus bridge, and clock generator. However, the block diagram issimplified for descriptive convenience, and it is to be understood thatthis block arrangement is not intended to limit the present invention.

The operation of the controller 103 will be explained by exemplifyingimage copying on a paper medium. When the user designates image copyingfrom the operation unit 105, the CPU 201 sends an original image readinginstruction to the scanner device 102 via the CPU 221. The scannerdevice 102 optically scans a paper original, converts it into digitalimage data, and inputs the digital image data to the image processingunit 227 via the device controller 228. The image processing unit 227DMA-transfers the digital image data to the memory 223 via the CPU 221and temporarily saves it.

If the CPU 201 confirms that the digital image data is saved all or by apredetermined amount in the memory 223, it issues an image outputinstruction to the printer device 104 via the CPU 221. The CPU 221instructs the image processing unit 227 about the position (address) ofthe image data stored in the memory 223. The image data in the memory223 is transmitted to the printer device 104 via the image processingunit 227 and device controller 226 in accordance with a sync signal fromthe printer device 104. The printer device 104 prints the digital imagedata on a paper medium. When printing a plurality of copies, the CPU 201saves image data of the memory 223 in the hard disk 106. For the secondand subsequent copies, the image can be sent to the printer device 104without receiving the image from the scanner device 102.

<Arrangement of Power Switch>

Next, the arrangement of a power switch in the image processingapparatus 100 according to the embodiment will be explained withreference to FIG. 3. In FIG. 3, reference numeral 301 denotes a togglepower switch; 302, a power supply unit; 303, an AC/DC converter; and304, an AC power input unit. Reference numeral 305 denotes a power cablefor supplying DC power to the printer device 104. Reference numeral 306denotes a power cable for supplying power to the controller 103.Reference numeral 307 denotes a line which notifies the controller ofthe state of the toggle switch 301. Reference numeral 308 denotes apower remote signal capable of controlling an output from the AC/DCconverter. Reference numeral 309 denotes a power protection timer forreliably guaranteeing the stop of power supply until a predeterminedtime elapses after the toggle switch 301 is operated to stop powersupply. Reference numeral 310 denotes a remote line capable ofcontrolling an output from the AC/DC converter.

The operator can turn on/off the image processing apparatus 100 byoperating the toggle switch 301. In the ON state, the toggle switch 301is connected to the AC/DC converter and can control the energizationstate of the power supply. In the OFF state, the stop of the powersupply 306 is inhibited till the completion of system shutdown (endprocessing of the image processing apparatus 100) by the controller 103.More specifically, the state of the toggle switch 301 is notified viathe line 307, and after completing shutdown, the DC power supply 306 isstopped using the power remote signal 308. In this manner, the powersupply arrangement of the image processing apparatus 100 is the same asthat of a general device which needs to be shut down.

The toggle switch 301 is a switch which keeps mechanically holdingeither the ON or OFF state. The operator can input a power supply stateby flipping the switch to either the ON or OFF side. The timer 309measures the time in response to the OFF operation of the toggle switch301, changes the remote signal 310 after a predetermined time, and canforcibly stop an output from the AC/DC converter 303. That is, thispower supply has a function of measuring the time during which thetoggle switch 301 is OFF, and stopping the AC/DC converter 303 after apredetermined time to completely turn off the power supply of theapparatus after a predetermined time.

The controller 103 can turn off its power supply using the power remotesignal 308. In this case, to prevent a mismatch with the physical OFF/ONstate of the toggle switch 301, when the controller 103 is notified ofthe power-off via the line 307, it can automatically turn off the toggleswitch 301 with a solenoid using an electromagnet or the like.

More specifically, supply of power from the power supply shown in FIG. 3to the “controller 103, printer device 104, and scanner device 102” isstopped by two methods: (1) the controller 103 receives the OFFoperation of the switch 301 via the line 307, and turns off the powersupply of the “controller 103, printer device 104, and scanner device102” using the power remote signal 308 after shutdown; and (2) the timer309 measures the OFF state of the switch for a predetermined time (120s), and if no OFF operation occurs in the power remote signal 308 tillthe lapse of the predetermined time (120 s), the remote control signal310 changes to turn off the power supply of the “controller 103, printerdevice 104, and scanner device 102”. Method (2) provides a powerprotection circuit for preventing a state in which the power supply ofthe “controller 103, printer device 104, and scanner device 102” is notturned off though the toggle switch 301 is turned off.

<Processing Sequence upon Shutdown>

A processing sequence when the toggle switch 301 is turned off will beexplained with reference to FIG. 4. An operation when the operator endsthe main body will be described. Upon detecting that the toggle switch301 serving as a main body power switch has been turned off, the CPU 201executes the following processing. At this time, the power protectiontimer 309 starts time measurement for the power protection circuit. Thefollowing processing is implemented by reading out, to the memory 203, acontrol program stored in the nonvolatile memory 205, HDD 106, or thelike and executing it by the CPU 201.

In step S401, when the toggle switch 301 is turned off, the CPU 201displays on the operation unit 105 a screen representing that the systemis being ended. In step S402, the CPU 201 performs interrupt/endprocessing for a running service and the like. Since the end processingis executed parallelly by a plurality of processes, the CPU 201determines in step S403 whether the end processing has been completed.If the end processing has been completed, the process advances to stepS404; if it has not been completed, the CPU 201 periodically repeats thedetermination in step S403.

In step S404, the CPU 201 synchronizes (SYNC) a memory value with thestorage. “Synchronize (SYNC)” means processing of storing, in thestorage, for example, the contents of a storage buffer cached in a DRAMin order to synchronize the contents of the buffer with the storage. Instep S405, the CPU 201 calls the shutdown I/F of the kernel and performssoftware final end processing of the kernel. Afterwards, in step S406,the CPU 201 turns off the AC/DC converter 303 using the power remotesignal 308, thereby turning off the power supply of the overallapparatus. Since the power supply of the overall apparatus is turnedoff, the power supply of the timer 309 itself is also turned off, andthe power protection timer stops its function.

If any processing in the flowchart shown in FIG. 4 stops due to anytrouble, the controller 103 does not change the power remote signal 308.In this case, however, the timer 309 stops an output from the AC/DCconverter 303 using the remote control signal 310, thereby forciblyturning off the power supply.

<Hibernation>

A hibernation method used in the embodiment will be explained withreference to FIG. 5. Hibernation is a function of saving a stateimmediately before the power supply of the apparatus is turned off, andwhen the power supply is turned on the next time, restarting theoperation from the state immediately before the power supply is turnedoff. To use hibernation at the time of power-off, the state (contents)of a predetermined memory at the time of power-off needs to be held. Ageneral kernel running on the CPU 201 manages the memory 203 by “page”for every predetermined size. The page takes two states:

A. memory in a discard-permitted state (invalid memory)

B. memory in a discard-inhibited state (valid memory)

A represents a page for which it is known that its contents aresynchronized with an external disk while the memory operates as a diskcache, or an unused memory. B represents a state in which a changerequest from the user to an external disk is cached in the memory, butthe contents have not been synchronized yet, or the memory of the kernelitself. Since memory A can be discarded, it suffices to save only memoryB as a hibernation target. Some kernels allow deleting even a validmemory in which 0s are stored in the entire area. A valid memory pagedetermination unit 510 functions as a selection means, and determines avalid memory. However, the determination condition changes depending onthe type and system of kernel.

In the embodiment, 501 to 503, 505, and 506 out of memories 501 to 509serve as valid memories B. By saving only valid memoires in the diskusing the hibernation method and returning them, the image processingapparatus 100 can return to a previous state. Hibernation is executed intwo ways, that is, almost performed by a BIOS, or controlled bysoftware. The former method needs to save and return all memory areasbecause there is no means for restricting valid memories. Thus, thelatter method is becoming a recent mainstream. Since the latter methodruns within the kernel, hibernation processing can end within a shorttime by saving and returning only a necessary portion of the memory.Recently, the latter soft hibernation method (to be referred to as softhibernation hereinafter in the embodiment) is frequently adopted.Although the embodiment will be explained based on the soft hibernationmethod, the present invention does not limit the hibernation method.

<Hibernation Shift Processing>

Shift processing when hibernation ends will be explained with referenceto FIG. 6. The shift processing will be explained using the exampleshown in FIG. 5. The following processing is implemented by reading out,to the memory 203, a control program stored in the nonvolatile memory205, HDD 106, or the like and executing it by the CPU 201.

After the start of hibernation shift processing, the CPU 201 outputs amessage “during system end processing” on the operation unit 105 in stepS601. In step S602, the CPU 201 interrupts the driver of a currentlyoperating hardware device to stop its operation in order to turn off thepower supply of the board.

In step S603, the CPU 201 sequentially reads 501 to 509 of the memory203, and the valid memory page determination unit 510 determines only anecessary memory. In FIG. 5, valid memories are 501 to 503, 505, and506. In step S604, the CPU 201 generates valid memory page managementinformation. In the embodiment, the valid memory page managementinformation includes information about the start block in which a validmemory starts, and information about the number of blocks by which validmemory blocks continue, as represented by 511. In addition to these twopieces of information, the management information may containinformation, as needed, such as the address of a physical memory, anaddress in a virtual memory, the application purpose of the memory, anda save position in the storage. The valid memory page managementinformation in the embodiment means management information for referringto a memory block retracted to the storage in order to restore it in themain memory.

In step S605, the CPU 201 saves memories of three blocks starting from501 in the flash disk 207 via the disk controller 206 in accordancewith, for example, information represented by 512 serving as one elementof the valid memory page management information. In step S606, the CPU201 loops the processing until all memory blocks which are listed in thevalid memory page management information and need to be retracted aresaved. Data transfer as represented by 513 is generated from the memory203 in accordance with 511.

After completing the processing of retracting all valid memories to theflash disk 207, the CPU 201 saves the valid memory page managementinformation 511 itself in step S607, and synchronizes all memory valueswith the storage (flash disk 207) in step S608. After that, the CPU 201turns off the power supply of the system using the power remote signal308.

<Secondary Storage Device>

A memory map on the flash disk 207 serving as a secondary storage devicewill be explained with reference to FIG. 7. Reference numeral 701denotes an MBR (Master Boot Record); 702, a system loader; and 703,logical partitions. An area 704 is defined for hibernation, and includesa hibernation header 705, a data area 706, and valid memory pagemanagement information 707. The data area 706 stores pieces ofinformation contained in the memories 501 to 503, 505, and 506. Notethat this memory map is merely an example, and is not intended to limitthe present invention.

<Timing Chart>

A case 820 in which hibernation shift processing is normally performed,and a case 810 in which forcible power-off of the CPU 201 occurs will beexplained with reference to FIG. 8. First, the case 810 will bedescribed. Reference numeral 801 denotes a count-up state of the powerprotection timer 309 in FIG. 3. Reference numeral 802 denotes a voltageoutput from the AC/DC converter 303. Reference numeral 803 denotes acontent of processing executed by the CPU 201 in FIG. 2. The abscissarepresents the time. The operation states 801 to 803 are described froma timing 800 when the toggle switch 301 is turned off.

When the operator turns off the toggle switch 301 at the timing 800, thepower protection timer 309 starts counting up in order to protect thepower supply. In the embodiment, the measurement time of the powerprotection timer 309 is set to 120 sec. That is, the embodimentguarantees power-off after 120 sec.

As represented by 803, the CPU 201 executes system interrupt processing(hibernation shift processing) described with reference to FIG. 6. Thepower protection timer 309 measures 120 sec to protect the power supply.If system interrupt processing by the CPU 201 (Case 1) requires 120 secor longer, as represented by 803, the remote control signal 310 isdisabled at a timing 804, and power supply to the AC/DC converter 303 in802 stops. In response to this, the power supply of the controller 103is turned off, and the power supply is forcibly turned off though theCPU 201 executes hibernation processing. Hibernation stops while thestorage is accessed to write a memory value in the storage, so data inthe storage may be damaged.

Next, the case 820 will be explained. When system interrupt processingby the CPU 201 (Case 2) ends within 120 sec, shutdown 807 is executed,the power supply of the AC/DC converter 303 can be spontaneously turnedoff after completing hibernation processing, and the system normallyends, as represented by 806.

A plurality of varying factors exist for the time taken for hibernationshift processing, and the range of variation is large. Examples of thefactors are

-   -   a great increase in the amount of data subjected to hibernation        as the memory 203 gets dirty    -   a temporary decrease in storage access speed in write in the        data area 706. When a delay arises from an external device, the        time required is not known before actually accessing the        external device, and cannot be calculated in advance.

<Processing Sequence>

The present invention proposes a hibernation shift processing method ina situation in which the apparatus needs to end within a predeterminedtime, as described above. A processing sequence and timing when thetoggle switch 301 in the present invention is turned off will beexplained with reference to FIGS. 9 to 11. FIG. 9 is a timing chart whenhibernation shift processing in the embodiment is executed. FIG. 11shows the processing sequence of hibernation shift processing in theembodiment. The following processing is implemented by reading out, tothe memory 203, a control program stored in the nonvolatile memory 205,HDD 106, or the like and executing it by the CPU 201.

In FIG. 9, reference numeral 901 denotes a count-up state of the powerprotection timer 309. The ordinate of a graph 902 normalizes, to 100,the progress of all pages which need to be written in the data area 706while the CPU 201 executes the processes in steps S606 and S607. Thatis, the ordinate forms a graph representing the progress of saveprocessing of data to be written in the data area 706.

When the operator turns off the toggle switch 301, a flowchart 1101 inFIG. 11 is executed according to the embodiment. The CPU 201 activates ahibernation shift processing task (task which executes the flowchart ofFIG. 6) in step S1102, and activates a system protection timer task(task which executes a flowchart 1121 in FIG. 11) in step S1103.Further, the CPU 201 activates a hibernation progress management task(task which executes a flowchart 1111 in FIG. 11) in step S1104, andends the processing. These three flowcharts are executed virtuallyparallelly on the CPU 201 by independent threads.

As described above, in the flowchart of FIG. 6, all memory pagessubjected to hibernation are calculated and sequentially written in thedata area 706. After completing the write, hibernation shift processingis executed to perform shutdown. The flowchart 1111 is executed by atask which operates parallelly even during execution of the hibernationprocessing and manages the progress of hibernation. More specifically,it is monitored whether the flowchart in FIG. 6 will be completed bytarget time 909.

First, a normal end case in which hibernation save processing(hibernation processing) executed in the flowchart of FIG. 6 isperformed as indicated by a solid line 910 in FIG. 9 will be explainedwith reference to the flowchart 1111. In step S1112, the CPU 201 waitsfor a predetermined time 903. In step S1113, the CPU 201 acquires thetime t (point on the abscissa of the graph 902) elapsed until now. Instep S1114, the CPU 201 acquires a total page count in the memory pageand a currently ended page count.

In step S1115, the CPU 201 determines whether memory page saveprocessing in the current hibernation will be completed by the targettime 909. Although there are various calculation methods, the progresscan be calculated using, for example, the following equation:

progress=(number of written memory pages)/(number of memory pages whichneed to be written)*100  (1)

According to equation (1), the progress [%] at the current time t alongthe ordinate of the graph 902, that is, when the completion of writeprocessing is defined as 100% can be obtained.

In step S1116, whether memory page save processing will be completed bythe target time 909 on the current progress is determined using thefollowing conditional expression:

(progress*target time 909)/t>100  (2)

By evaluation expression (2), it can be determined whether hibernationsave processing will be completed by the target time 909.

For the solid line 910, it can be predicted that save processing willprogress as indicated by a broken line 912. It is therefore determinedthat save processing for all pages will be completed by the target time909. The process returns to wait processing in step S1112. After thewait in step S1112, the same evaluation is performed again. The loopprocessing is repeated several times, and if no problem occurs, the saveprocessing progresses as indicated by the broken line 912. The storageis synchronized in the processing of step S608, the AC/DC converter 303is turned off, and the power supply of the board is turned off. This isthe processing sequence in the normal case.

Next, a hibernation interrupt/end case in which hibernation saveprocessing in the flowchart of FIG. 6 is performed as indicated by asolid line 911 will be described. Similar to the case as indicated bythe solid line 910, steps S1112 to S1116 are executed. After calculationin step S1116 is performed, it can be predicted that the processing willnot be completed by the target time 909 on the current progress. Thus,the process advances to step S1117, and the CPU 201 interrupts thehibernation processing in the flowchart of FIG. 6, and processesinformation in the hibernation areas 705 to 707 (for example, discardsintermediate data). Subsequently, in step S1118, the CPU 201 functionsas a power control means, shuts down the system, and turns off the powersupply. This is a shutdown operation 907 in FIG. 9. The power supply ofthe board is turned off after completing shutdown, as represented by908.

In this way, when hibernation save processing is not completed within apredetermined time, the present invention can be practiced to end thesystem within a short time without waiting till the target time 909. Byproperly setting the target time 909, a risk that the power supply isturned off during the hibernation operation can be avoided even for apower supply source externally equipped within a timer device configuredto forcibly turn off the power supply.

This method becomes valid when processing by the CPU 201 which performshibernation processing operates normally. In some cases, the flowchart1111 may not operate normally, or a process which is executinghibernation may freeze and not operate at a timing 1003 shown in FIG.10. In such a case, the processes in steps S1116 to S1118 are neitherdetermined nor executed, and the power supply is forcibly turned off. Toprevent this, the embodiment provides a mechanism for normally endinghibernation by a system protection timer task even in these abnormalstates. Detailed processing will be explained with reference to thetiming chart of FIG. 10 and the flowchart 1121 of FIG. 11.

First, in step S1122, the CPU 201 sets the system protection timer 210.The time is set to satisfy

time of timer 210<(time of timer 309−time of shutdown 1005)

time of timer 210>(target time 909+time of shutdown 1005)  (3)

More specifically, the time (second time) set in the timer 210 is set tobe shorter than the time obtained by subtracting the time necessary forshutdown processing from the time (first time) set in the timer 309, andlonger than the time obtained by adding the time necessary for shutdownprocessing to the target time 909. With these settings, even when anevent is issued to the CPU 201 before the lapse of the time of the timer309 and the shutdown processing 1005 is performed upon receiving theevent, it can be controlled to complete hibernation processing by thetime of the power protection timer 309. In step S1122, the set time ofthe timer 210 that is obtained from the conditions of expressions (3) isset.

In step S1123, the CPU 201 determines whether an interrupt of the timer210 has occurred. If no interrupt has occurred, the determination instep S1123 is periodically repeated. If an interrupt has occurred, theprocess advances to step S1124. If the timer 210 expires at a timing1004 in FIG. 10, the process advances to step S1124. The CPU 201functions as a forcible end means, performs the shutdown processing1005, and then turns off the power supply of the board before the timeof the power protection timer 309 expires. This control is built in aprocess different from a process (software resource) which executeshibernation, or a system which operates in a privileged mode such as akernel mode. Accordingly, normal end processing of the system can beexecuted further forcibly.

According to the embodiment, when no hibernation is performed, a coldboot of the system is performed in the next power-on operation.Therefore, the apparatus cannot return to a state immediately before theprevious end, and the startup time becomes long. However, the apparatuscan be controlled normally.

As described above, according to the embodiment, data save processing ofhibernation having a large time variation factor can be safely performedin an image processing apparatus including a time-limit timer whichforcibly stops power supply from the outside in response to the OFFoperation of the toggle switch 301 as a trigger. If data save processingwill not be completed in time, it can be abandoned in a minimum time.This can shorten the time (system end time) until the power supply isactually turned off upon switch-off.

Other Embodiments

Aspects of the present invention can also be realized by a computer of asystem or apparatus (or devices such as a CPU or MPU) that reads out andexecutes a program recorded on a memory device to perform the functionsof the above-described embodiment(s), and by a method, the steps ofwhich are performed by a computer of a system or apparatus by, forexample, reading out and executing a program recorded on a memory deviceto perform the functions of the above-described embodiment(s). For thispurpose, the program is provided to the computer for example via anetwork or from a recording medium of various types serving as thememory device (for example, computer-readable medium).

While the present invention has been described with reference toexemplary embodiments, it is to be understood that the invention is notlimited to the disclosed exemplary embodiments. The scope of thefollowing claims is to be accorded the broadest interpretation so as toencompass all such modifications and equivalent structures andfunctions.

This application claims the benefit of Japanese Patent Application No.2011-270616 filed on Dec. 9, 2011, which is hereby incorporated byreference herein in its entirety.

1.-8. (canceled)
 9. An image processing apparatus, comprising: a powerswitch; a storing unit configured to store settings of a pre-setprocessing which the image processing apparatus executes in a case wherean operation to turn off the power switch is detected; a power stoppingunit that forcibly stops power supply to the image processing apparatuswhen a first time has elapsed after the power switch is operated; aprocessing unit that executes the pre-set processing to retract, in asecond storage unit, a stored content of a first storage unit used as awork area by a CPU of the image processing apparatus in a case where thepower switch is operated; a determination unit that determines, afterstarting the pre-set processing, whether or not the pre-set processingby the processing unit will be completed before the first time elapses;and a control unit that, in a case where the determination unit hasdetermined that the pre-set processing is not completed before the firsttime elapses executes a shutdown processing of the image processingapparatus.
 10. The apparatus according to claim 9, wherein theprocessing unit comprises: a selection unit that selects, from aplurality of memory blocks of the first storage unit, a memory blockwhose stored content is to be retracted to the second storage unit, ageneration unit that generates management information representinginformation of the memory block selected by the selection unit, and aretraction unit that stores, in the second storage unit, the storedcontent of the memory block selected by the selection unit, and themanagement information generated by the generation unit.
 11. Theapparatus according to claim 10, wherein the determination unitdetermines, by referring to the management information generated by thegeneration unit, whether or not the pre-set processing by the processingunit will be completed within the target time.
 12. The apparatusaccording to claim 9, further comprising: a timer unit that times a timeelapsed after operating the power switch, and wherein the control unit,when the timer unit times a second time shorter than the first time,executes the shutdown processing of the image processing apparatus. 13.A method for controlling an image processing apparatus comprising apower switch, comprising: storing settings of a pre-set processing whichthe image processing apparatus executes in a case where an operation toturn off the power switch is detected; forcibly stopping power supply tothe image processing apparatus when a first time has elapsed after thepower switch is operated; executing pre-set processing to retract, in asecond storage unit, a stored content of a first storage unit used as awork area by a CPU of the image processing apparatus in a case where thepower switch is operated; determining, after starting the pre-setprocessing, whether or not the pre-set processing will be completedbefore the first time elapses; and executing, in a case where it hasbeen determined that the pre-set processing is not completed before thefirst time elapses, the shutdown processing of the image processingapparatus.
 14. A non-transitory computer-readable storage medium storinga computer program for causing a computer to execute each step in animage processing apparatus control method, the method comprising:storing settings of a pre-set processing which the image processingapparatus executes in a case where an operation to turn off the powerswitch is detected; forcibly stopping power supply to the imageprocessing apparatus when a first time has elapsed after the powerswitch is operated; executing pre-set processing to retract, in a secondstorage unit, a stored content of a first storage unit used as a workarea by a CPU of the image processing apparatus in a case where thepower switch is operated; determining, after starting the pre-setprocessing, whether or not the pre-set processing will be completedbefore the first time elapses; and executing, in a case where it hasbeen determined that the pre-set processing is not completed before thefirst time elapses, the shutdown processing of the image processingapparatus.
 15. The apparatus according to claim 9, further comprising anactivation unit that executes a cold boot in a case where the imageprocessing apparatus which the shut down processing is executed isactivated.
 16. The apparatus according to claim 9, wherein thedetermination unit determines whether or not the pre-set processing bythe processing unit will be completed before the first time elapses,based on a time period elapsed after starting the pre-set processing anda progress of the pre-set processing executed in the elapsed timeperiod.